High spatial resolution monolithic pixel detector in SOI technology

This paper presents test-beam results of monolithic pixel detector prototypes fabricated in 200 nm Silicon-On-Insulator (SOI) CMOS technology studied the context high spatial resolution performance. The tested detectors were on a 500 μm thick high-resistivity Floating Zone type n (FZ-n) wafer and 300 Double SOI Czochralski p (DSOI Cz-p) wafer. size is 30 × two different front-end electronics architectures tested, source follower charge-sensitive preamplifier. data analyses focused mainly determination hit detection efficiency. In this work cluster formation position reconstruction methods are studied. particular, generalization standard η-correction adapted for arbitrary sizes, introduced. obtained give best case about 1.5 FZ-n 3.0 DSOI Cz-p wafer, both showing efficiency above 99.5%.